1. Field of the Invention
The invention relates to a method for operating a non-volatile flash memory, and more particularly to a programming and erasing method for a localized charge trapping memory using a high density multi-level cell.
2. Description of the Related Art
Presently, non-volatile flash memory devices have been widely used for portable electronics, such as MP3 players, digital cameras, personal digital assistants, mobile phones and laptop computers, etc. High-capacity and low-cost flash memory devices are in great demand. Thus, increasing the storage capacity and reducing the manufacturing cost become the main targets for the memory manufacturers. As the memory fabrication approaches physical limits in terms of device miniaturization increasing the memory density of devices by simply scaling down the size of the memory cell becomes more and more difficult. By contrast, the more effective method to increase the storage capacity is to apply multi-level cell (MLC) techniques, which have attracted much research efforts in recent years. Unlike a single-level cell (SLC), which stores one bit in each cell, the MLC can store multiple bits in each cell. In this method, the bit state stored in the memory is characterized by the number of charges, using charge carriers to change the threshold voltage of the memory cell and read the value of the current to determine the stored bits. In order to accurately read out the stored bits, threshold voltage distributions of a programmed state need to be spaced apart from each other. Limited by the whole memory window, if MLC device achieves more than 3 bits/cell storage, the allowable distribution width of each state is very narrow and the spacing between different threshold voltage distributions is also very narrow. Moreover, the current memory programming methods cannot program the memory cell to the precise threshold level. Therefore, different threshold levels tend to overlap so that bit state determination becomes very difficult. Moreover, due to the narrow threshold voltage distribution width of each state, the degradation of program/erase cycling endurance and retention for the memory with MLC become problematic. Therefore, the reliability issues of MLC limit the further applications of MLC technique.
Localized charge trapping polysilicon-oxide-nitride-oxide-silicon (SONOS) can locally store 1 bit at source and drain side of each memory cell, respectively. NROM as a typical localized trapping SONOS memory device achieves 2 bits, referred to U.S. Pat. No. 7,110,300. If NROM cell uses four-level storage at the each side of cell, it can realize 4 bits storage per cell, which greatly increases the storage capacity and reduces the cost. The initial threshold voltage of NROM is about 2-3V and the highest programmed threshold voltage is about 5-6V. So, the whole memory window limits to about 3 V. If NROM achieves 3 bits storage at the each side of cell, there will be eight threshold levels in a 3 V memory window. Thus, the allowable threshold voltage distribution width of each state is less than 0.3 V. It is difficult to program the NROM cell to such a precise threshold level by using the conventional channel hot electron (CHE) injection programming technique.
Since it is difficult to achieve more than 8-level 3 bits high density storage at the each side of memory cell using the traditional MLC operating method, it is very urgent to invent new multi-level cell operating methods to increase storage density. Meanwhile, it is also an important subject to improve the accuracy of program/erase operation and increase the reliability of MLC operation, i.e. program/erase cycling endurance and retention.